1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a static type semiconductor memory device. More specifically, the present invention relates to a structure of a bit line precharge/equalize circuit of a static random access memory.
2. Description of the Background Art
FIG. 21 schematically shows a structure of an array portion of a conventional static semiconductor memory device. The structure of a static random access memory (SRAM) as the static type semiconductor memory device shown in FIG. 21 is described, for example, in Japanese Patent Laying-Open No. 7-226083.
In FIG. 21, the SRAM includes a plurality of memory cells M arranged in a matrix, a plurality of word lines WL each arranged corresponding to a row of memory cells and connecting memory cells of a corresponding row, and a plurality of pairs of bit lines BL, /BL each arranged corresponding to a column of memory cells and connecting memory cells of a corresponding column. FIG. 21 representatively shows a word line WL1, bit line pairs BL1, /BL1-BLn, /BLn, and memory cells M1-Mn arranged corresponding to the crossings of word line WL1 and bit line pairs BL1, /BL1-BLn, /BLn.
Memory cells M1-Mn each include an inverter latch formed of inverters 202 and 203 for storing complementary data in storage nodes SN and /SN, and access transistors 204 and 205 rendered conductive to connect storage nodes SN and /SN to corresponding bit lines BL, /BL (BL1, /BL1-BLn, /BLn) in response to a signal potential of word line WL (WL1). Access transistors 204 and 205 are n channel MOS transistors (insulated gate type field effect transistors).
The SRAM further includes: bit line precharge/equalize circuits BEQ1-BEQn provided corresponding to respective bit line pairs BL1, /BL1-BLn, /BLn, and activated upon activation of a bit line equalize instruction signal /EQ for precharging and equalizing corresponding bit line pairs BL1, /BL1-BL1n, /BLn to a power supply voltage Vcc level; column selection gates CSG1-CSGn provided corresponding to respective bit line pairs BL1, BL1-BLn, /BLn, receiving a column selection signal Y (Y1-Yn) from a column decoder, not shown, and rendered conductive to electrically connect a corresponding bit line pair to internal read data bus lines DB, /DB when the received column selection signal designates the corresponding bit line pair; and a sense amplifier 215 activated at the time of data reading, for amplifying the signal potentials of internal read data bus lines DB, /DB to generate internal read data, and transferring them to a data output circuit, not shown.
Bit line precharge/equalize circuits BEQ1-BEQn each include a p channel MOS transistor 206 rendered conductive to transfer a power supply voltage Vcc to bit line BL (BL1-BLn) when bit line equalize instruction signal /EQ is activated, a p channel MOS transistor 207 rendered conductive to transfer the power supply voltage Vcc to bit line /BL (/BL1-/BLn) when bit line equalize instruction signal /EQ is activated, and a p channel MOS transistor 208 rendered conductive to electrically connect bit lines BL and /BL when bit line equalize instruction signal /EQ is activated.
Column selection gates CSG1-CSGn each include an inverter circuit 210 inverting column selection signal Y (Y1-Yn), a CMOS transmission gate 211 rendered conductive to connect corresponding bit line BL (BL1-BLn) to internal read data bus line DB in accordance with column selection signal Y1 and an output signal from inverter circuit 210, and a CMOS transmission gate 212 rendered conductive to connect corresponding bit line /BL (/BL1-/BLn) to internal read data bus line /DB in accordance with column selection signal Y1 and the output signal from inverter circuit 210.
Sense amplifier 215 includes a structure of a differential amplifier circuit and generates internal read data by differentially amplifying complementary data which appear on internal read data bus lines DB and /DB. Now, the data reading operation of the SRAM shown in FIG. 21 will be described with reference to a waveform diagram shown in FIG. 22.
At the time of data reading, bit line equalize instruction signal /EQ is at an H level inactive state. By driving bit line equalize/precharge circuits BEQ1-BEQn to an inactive state at the time of data reading, an accurate data reading is accomplished.
When an address signal is applied, a row decoder and a column decoder which are not shown operate in accordance with this applied address signal, and a word line corresponding to an addressed row and column selection signal Y corresponding to an addressed column are driven to the selected state. As an example, FIG. 22 shows the case in which word line WL1 is selected. In accordance with a rise of the potential of word line WL1, respective access transistors 204 and 205 of memory cells M1-Mn which are connected to this word line WL1 are rendered conductive, and storage nodes SN and /SN are connected to corresponding bit lines BL and /BL (BL1, BL1-BLn, /BLn).
When corresponding memory cells are not selected, bit line precharge/equalize circuits BEQ1-BEQn are active and they supply current to corresponding bit lines. On the other hand, bit line precharge/equalize circuits BEQ1-BEQn are inactivated when their corresponding memory cells are selected. The current which has been supplied from bit line precharge/equalize circuits BEQ1-BEQn to each bit line flows in the storage nodes storing an L level in memory cells M1-Mn, causing a potential difference between bit lines BL and /BL.
Along with row selection, a bit line pair corresponding to a selected column is connected to read data bus lines DB, /DB in accordance with column selection signal Y. Storage nodes SN and /SN hold complementary data. Now, the case is assumed in which memory cell M1 is selected and its storage node SN stores data of an H level. In this case, current (column current) flows from bit line /BL1 to storage node /SN of memory cell M1, and the voltage level of bit line BL1 is lowered. Meanwhile, storage node SN stores the H level and the voltage level of bit line BL1 is hardly changed.
The potential difference caused between bit lines BL1 and /BL1 is transferred through column selection gate CSG1 to internal read data bus lines DB, /DB. Sense amplifier 215 is activated at prescribed timing to amplify a potential difference caused between internal read data lines DB, /DB for generating internal read data.
When the reading operation of memory cell data is completed, the potential of selected word line WL1 is driven to the L level, and column selection signal Y1 also falls to the L level inactive state. Thus, bit lines BL1, /BL1 are isolated from internal read data bus lines DB, /DB. Since word line WL1 attains the non-selected state, access transistors 204 and 205 of memory cells M1-Mn are at the non-conductive state, and bit lines BL1, BL1-BLn, /BLn are precharged to their original power supply voltage Vcc level by corresponding bit line precharge/equalize circuits BEQ1-BEQn.
At the time of data writing, bit line equalize instruction signal /EQ is driven to the H level inactive state, and bit line precharge/equalize circuits BEQ1-BEQn are kept at the inactive state. When word line WL1 is selected, memory cells M1-Mn are connected to corresponding bit lines BL1, /BL1-BLn, /BLn. The potential of a bit line slightly changes according to data stored in memory cells M1-Mn. Along with word line selection, the column selection operation is performed. Column selection signal Y corresponding to a selected column is activated, and a bit line pair corresponding to the selected column is connected to a write circuit which is not shown. Further, complementary data are transferred from this write circuit to selected bit lines BL and /BL. As a result, data stored in storage nodes SN and /SN of a memory cell attain potential levels corresponding to the write data. After data writing is completed, as in the case of data reading, the word line is driven again to the non-selected state and column selection signal Y is also inactivated, thus ending the data writing operation. Then, bit line equalize instruction signal /EQ is activated to precharge the potentials of bit lines BL, /BL to their original power supply voltage level.
FIG. 23 shows an example of the specific structures of memory cells M1-Mn shown in FIG. 21. Since memory cells M1-Mn have the same structure, the reference character M is representatively used in FIG. 23.
In FIG. 23, memory cell M includes a high-resistance resistive element 220 connected between a power supply node supplying a power supply voltage Vcc and a storage node /SN, a driver transistor 221 formed of an n channel MOS transistor connected between storage node /SN and a ground node supplying a ground voltage GND and having its gate connected to a storage node SN, a high-resistance resistive element 222 connected between the power supply node and storage node SN, a driver transistor 223 connected between storage node SN and the ground node and having its gate connected to storage node /SN, and access transistor 204 formed of an n channel MOS transistor rendered conductive to connect storage node SN to bit line BL in response to the signal potential of word line WL, and an access transistor 205 formed of an n channel MOS transistor rendered conductive to connect storage node /SN to bit line /BL in response to the signal potential of word line WL.
High-resistance resistive element 220 and driver transistor 221 correspond to inverter 202 of the memory cell shown in FIG. 21, while high-resistance resistive element 222 and driver transistor 223 correspond to inverter 203 of the memory cell shown in FIG. 21. When H level data is stored in storage node SN, driver transistor 221 is on, and storage node ISN is kept at the ground potential level (the current drivability of high-resistance resistive element 220 is extremely low). Since storage node /SN is driven to the L level, driver transistor 223 is off, and storage nodes SN and /SN are kept at the H and L levels, respectively. If high-resistance resistive elements 220 and 222 are formed of polysilicon resistors, for example, high-resistance resistive elements 220 and 222 can be formed in an upper layer of respective driver transistors 221 and 223. As a result, the area occupied by the memory cell can be reduced.
The resistance value of a high-resistance resistive element is sufficiently larger than the ON resistance (channel resistance) of access transistors 204 and 205 as well as that of driver transistors 221 and 223. Therefore, when word line WL is selected and thus access transistors 204 and 205 are rendered conductive, the transfer factor .beta.b (the ratio of a channel width Wb and a channel length Lb) of driver transistors 221 and 223 has to be set to be more than three times the transfer factor .beta. of access transistors 204 and 205 in order to reliably hold stored data in storage nodes SN and /SN, as described below in detail. The reason why the transfer factor of a driver transistor should be larger than the transfer factor of an access transistor in order to reliably hold memory cell data will be described below.
The input/output characteristic of an inverter I as shown in FIG. 24A will be discussed here. Inverter I inverts an input signal IN and generates an output signal OUT. Therefore, the input/output characteristic of inverter I is represented by a curve as shown in FIG. 24B. Since output signal OUT makes a quick transition according to a transition of input signal IN as the gain of inverter I becomes larger, the transition of the input/output characteristic curve shown in FIG. 24 becomes steeper. The gain of inverter I is determined by the current drivability of its components, MOS transistors.
As shown in FIG. 25A, a memory cell of an SRAM stores data in its storage nodes SN and /SN by an inverter latch. Here, inverter 202 inverts the signal potential of storage node SN for transference to storage node /SN, while inverter 203 inverts the signal potential of storage node /SN for transference to storage node SN. When inverters 202 and 203 have the same input/output transfer characteristic, an input/output data characteristic curve which is axially symmetrical is obtained as shown in FIG. 25B. This axial symmetry indicates that input IN and output OUT of an inverter are the same.
In FIG. 25B, the abscissa denotes the signal potential of storage node SN and the ordinate denotes the potential of storage node /SN. Further, the curve A1 indicates the input/output transfer characteristic of inverter 202 and the curve A2 indicates that of inverter 203. The points S1 and S2 corresponding to the crossings of these curves A1 and A2 are stable points for this inverter latch. The voltages corresponding to one of these stable points S1 and S2 are provided at storage nodes SN and /SN.
In order to stably operate the inverter latch, the curves A1 and A2 shown in FIG. 25B require two stable points S1 and S2. The point PM is a meta-stable point. Even if the voltages provided to storage nodes SN and /SN are initially the voltages corresponding to the metastable point PM, the latched state will be shifted to the stable point SE1 or S2 due to some noise.
In order to ensure that the inverter latch formed of inverters 202 and 203 stably operates and reliably holds the potentials of storage nodes SN and /SN, the area surrounded by the curves A1 and A2 (static noise margin SNM) should be made larger. When this area ("eyes" of the characteristic curves) is small, the curves A1 and A2 come closer to each other and their adjacent point simulatively acts as a stable point. Therefore, an arbitrary intermediate potentials can be held as a stable point in storage nodes SN and /SN and correct data cannot be held.
In the structure of an inverter latch of a memory cell, the manner of connection varies according to the selected and non-selected states. Now, consider the manner of connection when SRAM memory cell M is at a standby state (where the word line is in the non-selected state) as shown in FIG. 26A. In the standby state, access transistors 204 and 205 are off as shown in FIG. 26A. In this state, storage nodes SN and /SN are connected through high-resistance resistive elements 222 and 220 to the power supply node. Inverter 202 is formed of resistive element 220 and driver transistor 221, while inverter 203 is formed of resistive element 222 and driver transistor 223. In the case of an inverter using this high-resistance resistive element, the conductive state of a driver transistor causes its output node to be discharged at high speed because the current supplying capability of the high-resistance resistive element is extremely low. In this case, therefore, the transfer characteristic curves A1 and A2 of inverters 202 and 203 come to have steep falls and rises as shown in FIG. 26B, and thus data is stably hold.
FIG. 27A shows connection of each transistor of a memory cell where the corresponding word line is selected. When the word line is selected, access transistors 204 and 205 are turned on and storage nodes SN and /SN are connected to corresponding bit lines BL and /BL. Bit lines BL and /BL are connected to a bit line load circuit which is a current source (precharge circuit), and current flows from a corresponding bit line to that storage node out of storage nodes SN and /SN which holds the L level potential.
Therefore, this state is equivalent to a structure in which a low impedance load is connected in parallel with the high-resistance resistive elements, and thus to a structure in which high-resistance resistive elements 220 and 222 do not exist. In this state, inverters 202 and 203 should be treated as NMOS enhancement load type inverters using access transistors 204 and 205 as a load. As compared with the structure using the high-resistance resistive elements, the transition of a transition part of the input/output transfer characteristic curve is moderate and the gain of an inverter decreases, because current is supplied from the NMOS enhancement load type transistors. As shown in FIG. 27B, therefore, the area formed by the curves A1 and A2 becomes smaller and the static noise margin is accordingly reduced.
Then, consider the case in which access transistors 204 and 205 and driver transistors 221 and 223 have the same current drivability. In this case, the amount of current discharged from a conductive driver transistor (for example, transistor 223) is equal to the amount of current supplied to an access transistor (for example, transistor 204), and the input/output transfer characteristic of inverters 202 and 203 becomes quite moderate. As shown in FIG. 27C, this state comes to be closer to the state in which the curves A1 and A2 have only one stable point. In short, when an access transistor and a driver transistor have the same current drivability, the conductance of the access transistor and that of the driver transistor which holds the L level data are the same when a word line is selected. Thus, the potential of a storage node holding this L level is increased, which starts to render conductive the other driver transistor holding the H level, thus decreasing the potential of a storage node storing this H level. In this case, the stored data is destructed upon word line selection.
Stable points S1 and S2 are the operational points of a flipflop formed of these inverters, and this flipflop is held at either stable point. Therefore, when the input/output transfer characteristic makes a transition as shown in FIG. 27C, there is no bi-stable point and this leads to destruction of data stored in storage node SN and ISN at the time of word line selection. In order to ensure that the two stable points exist even at the time of word line selection, it is necessary to prevent the potentials of storage nodes SN and /SN from shifting to an intermediate potential level. In other words, it is necessary to reduce the ratio of the current drivability (conductance) of an access transistor and the current drivability (conductance) of a driver transistor.
Normally, the current drivability of a driver transistor is set three times as large as that of an access transistor. The current drivability (conductance) of an MOS transistor is proportional to the ratio .beta. of a channel width W and a channel length L. Destruction of stored data at the time of data reading is prevented by setting the ratio (cell ratio) of the current drivability to the value of 3 or 4 and ensuring that the input/output transfer characteristic of an inverter is comparatively steep even at the time of word line selection and that two stable points exist.
In order to ensure that the transfer factor .beta. of driver transistors 221 and 223 is larger than that of access transistors 204 and 205, the channel width of driver transistors 221 and 223 should be larger than that of access transistors 204 and 205. If only their respective channel length is reduced, it causes a short channel effect lowering a threshold voltage and an increased current consumption. Further, the size of driver transistors becomes large. Therefore, the memory size (occupied area) cannot be reduced and it becomes an obstacle against higher integration.
Further, at the time of data reading, current (column current) always flows from a bit line to a memory cell connected to a selected word line, and thus current consumption at the time of data reading is undesirably large.
The operational power supply voltage tends to be lowered because of high speed operation and low current consumption. An MOS transistor can supply a larger drain current as its gate voltage becomes higher. This is apparent because the drain current of MOS transistor which is in a saturated region can be represented by the following expression. EQU Ids=.beta.(Vgs-Vth).sup.2
Here, Vgs is a gate-to-source voltage, and Vth is a threshold voltage. Therefore, when the power supply voltage is lowered, the gate-to-source voltage Vgs is also lowered, decreasing the amount of driving current. Thus, when the operational power supply voltage is lowered, the input/output transfer characteristic of an inverter is moderate in its transition, and the input/output transfer characteristic as shown in FIG. 27C is provided and stored data is destroyed at the time of data reading (word line selection).
Since current is always supplied through a resistive element especially in an SRAM memory cell, the threshold voltage of driver transistors 221 and 223 is set higher than that of access transistors so as to minimize the current consumption. Therefore, when the operational power supply voltage is lowered, a difference between the current drivability of driver transistors 221 and 223 and the current drivability of access transistors 204 and 205 when rendered conductive is decreased, and the condition that the cell ratio is set to the value of 3 or 4 cannot be satisfied. In this case, a transition of the curves A1 and A2 is very moderate as shown in FIG. 27D. Therefore, there is no stable point but a pseudo stable point. Stored data is destroyed at the time of word line selection, thus preventing correct data reading.